Responsibilities:
•Design full custom analog IC Mask layout from floorplan to top/chip level layout
•Perform physical verification checking and debugging: LVS, DRC, etc.
•Closely work with project leader or directly with circuit engineer to implement optimum mask layout designs
•Generate/document necessary reports and assist activities until tapeout
Requirements:
•BS Electronics Engineering or Computer Engineering
• Have at least five (5) years of experience in full custom analog IC mask layout design from any semiconductor design company either local or abroad
•Adept in all the stages of IC mask design, from chip floorplanning, block layout, chip consolidation, layout verification, design reviews until tapeout
•Good understanding of the different layout considerations: matching, shielding, guardrings, latch-up,
•electron-migration, IR drop, etc.
•Well versed in using any EDA tool specific for IC mask designing
•Ability to estimate and make schedule plans for a given layout job
•Ability to work independently as well as within a dynamic team environment
•Excellent problem solving and analytical skills, adaptive to changes and has multi-tasking ability
•Above average oral and written communication skills, Japanese language skills is an advantage but not a requirement
•Customer-driven, always targets to exceed customer expectations